HT6576资料

••••

Support the ANSI X3.131-1986 standardAsynchronous transfer rate to 5 Mbyte/secSupport initiator and target mode0.8um CMOS process

•••On chip 48mA single-ended drivers andreceivers

Non internal clock needed44pins PLCC package

Block Diagram

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Pin Diagram

Pin Description

Host Interface SignalPin No14~161711924~28,20~221019188137Pin NameA0~A2CSDACKDRQD0~D7EOPIORIOWIRQREADYRESETI/OIIIOI/OIIIOOIAddress LinesChip Select, active lowDescriptionDMA Acknowledge, active lowDMA RequestData LinesEnd of Process, active low I/O Read, active lowI/O Write, active lowInterrupt RequestReadyReset, active low元器件交易网www.cecb2b.comHT6576ASCSI Interface SignalsPin No 3330322934237~41,43, 44, 1355VSS

Pin NameACKATNBSYC/DI/OMSGREQRSTDB0–DB7DBPSELI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/ODescriptionAcknowledge, active lowAttention, active lowBusy, active lowControl/Data, active lowInput/Output, active lowMessage, active lowRequest, active lowReset, active lowSCSI Data Bus, active lowSCSI Parity Bit, active lowSelect, active low3, 12, 31, 36, 42VDD

23

Registers

Address 0

Current SCSI data register(READ ONLY)DB7DB6DB5DB4DB3DB2DB1DB0The SCSI bus parity is checked at the beginning of the read cycle.Output data register(WRITE ONLY)DB7DB6DB5DB4DB3DB2DB1DB0314th July ’97

元器件交易网www.cecb2b.comHT6576AAddress 1: Initiator command register

WRITE

7 6 5 4 3 2 1 0 ASSERTTRI–STATERESERVEDRST•BIT 7: ASSERT RSTASSERTACKASSERTBSYASSERTSELASSERTATNASSERTDATAWHEN SET, THE RST SIGNAL IS ASSERTED ON THE SCSI BUS•BIT 6: TRI–STATE (TEST MODE)•BIT 5: RESERVED (0)•BIT 4: ASSERT ACKWHEN SET, THE ACK SIGNAL IS ASSERTED ON THE SCSI BUS•BIT 3: ASSERT BSY

WHEN SET, THE BSY SIGNAL IS ASSERTED ON THE SCSI BUS

•BIT 2: ASSERT SELWHEN SET, THE SEL SIGNAL IS ASSERTED ON THE SCSI BUS•BIT 1: ASSERT ATNWHEN SET, THE ATN SIGNAL IS ASSERTED ON THE SCSI BUS

•BIT 0: ASSERT DATA

WHEN SET, This bit allows the contents of the output data register to be enabled as chip outputson SCSI signal DB0–DB7READ

7 6 5 4 3 2 1 0 RETARBITPROGRESSLOSTARBITACKBSYSELATNASSERTDATAAddress 2: Mode register

READ/WRITE

7 6 5 4 3 2 1 0LOCKDMATARGETMODEENABLEPARITYENABLEPARITYENABLEEOPMONITORCHECKBUSYDMAIRQMODEARBIT•BIT 7: BLOCK MODE DMA•BIT 6: TARGET MODE

When set, the chip operates as an SCSI bus target device.

•BIT 5: ENABLE PARITY CHECKING

When set, data received on the SCSI data bus is checked for odd parity.

414th July ’97

元器件交易网www.cecb2b.comHT6576A•BIT 4: ENABLE PARITY INTERRUPT

When set, this bit causes the IRQ signal to be asserted if a parity error is detected.

•BIT 3: ENABLE EOP INTERRUPT

When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller.•BIT 2: MONITOR BUSY

When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for atleast a bus settle delay.

•BIT 1: DMA MODE•BIT 0: Arbitrate

When set, this bit starts the arbitration process.Address 3: Target command register

7 6 5 4 3 2 1 0 LAST BYTEXXXASSERTREQASSERTMSGASSERTC/DASSERTI/OR R/W R/W R/W R/W

•BIT 7: LAST BYTE SEND (READ ONLY)•BIT 3: ASSERT REQ

WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

•BIT 2: ASSERT MSGWHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)•BIT 1: ASSERT C/D

WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

•BIT 0: ASSERT I/O

WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE)Address 4: Current SCSI Bus Register

READ

7 6 5 4 3 2 1 0RSTBSYREQMSGC/DI/OSELDBPWRITE –SELECT ENABLE REGISTER

7 6 5 4 3 2 1 0SID7SID6SID5SID4SID3SID2SID1SID0514th July ’97

元器件交易网www.cecb2b.comHT6576AAddress 5: Bus And Status

READ

7 6 5 4 3 2 1 0ENDDMADMAREQUESTPARITYERRORIRQPHASEMATCHBUS ERRORATNACKWRITE –START DMA SEND

7 6 5 4 3 2 1 0XXXXXXXXAddress 6: Input Data

READ

7 6 5 4 3 2 1 0LDB7LDB6LDB5LDB4LDB3LDB2LDB1LDB0LATCH SCSI DATA. The register represent the complement of the active low SCSI data bus.WRITE –START DMA TARGET RECEIVE

7 6 5 4 3 2 1 0XAddress 7:

XXXXXXXREAD –RESET PARITY/INTERRUPT

7 6 5 4 3 2 1 0XXXXXXXXWRITE –START DMA INITIATOR RECEIVE

7 6 5 4 3 2 1 0XXXXXXXX614th July ’97

元器件交易网www.cecb2b.comHT6576AInterrupts

SELECTION/RESELECTION

•SEL= ACTIVE LOW•BSY IS FALSE FOR AT LEAST 400NS•HT6576A DEVICE ID (SELECT REGISTER) is active on the SCSI bus will generate IRQ.

END OF PROCESS (EOP) INTERRUPT

•EOP= ACTIVE LOW•DACK= ACTIVE LOW•IOR OR IOW= ACTIVE LOW•DMA MODE

•ENABLE EOP IRQ⇒ GENERATE EOP IRQ

SCSI BUS RST/IRQWhen An SCSI RST active low, the IRQ is generated.PARITY ERROR IRQ

An IRQ is generated for a received parity error if enable parity checking bit and the enableparity interrupt bit are set.BUS PHASE MISMATCH IRQ

If the DMA MODE bit is active and a phase mismatch occurs when REQ from false to true,an interrupt is generatedLOSS OF BSY/IRQ

•MONITOR BSY bit= 1

•BSY= ACTIVE LOW FOR 400ns WILL GENERATE IRQ714th July ’97

元器件交易网www.cecb2b.comHT6576AElectrical Characteristics

D.C. Characteristics

Absolute Maximum Ratings(Ta=25°C)

SymbolTstgVDDVINESDParameterStorage TemperatureSupply VoltageInput VoltageElectrostatic Discharge Min.–55–0.5VSS–0.5–5000Max.1507.0VDD+0.55000Unit°CVVV(Ta=25°C)

Operating Conditions

SymbolVDDIDDTaSCSI Signals

ParameterSupply VoltageSupply CurrentOperating Free-AirMin.4.75—0Max.5.252070UnitVmA°C(Ta=25°C)

SymbolVIHVILVOLVHYSIOLIIHIILCharacteristicInput High VoltageInput Low VoltageOutput Low VoltageHysteresisOutput Low CurrentInput High LeakageInput Low LeakageCondition——IOL=48mA—VOL=0.5VIH= 5.25VVIL=VSSMin.2.0VSS–0.5VSS20048——Max.VDD+0.50.80.5450—50–50UnitVVVmVmAµAµA814th July ’97

元器件交易网www.cecb2b.comHT6576AMicroprocessor Data Bus D0-D7

(Ta=25°C)

SymbolVIHVILVOHVOLIOHIOLIIHIILITLCharacteristicInput High VoltageInput Low VoltageOutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentInput High LeakageInput Low LeakageTri-State LeakageCondition——IOH=–4.0mAIOL=8.0mAVOH=VDD–0.5VVOL=0.4VVIH=5.25VVIL=VSS—Min.2.0VSS–0.52.4VSS–4.08.0——–10Max.VDD+0.50.8VDD0.4——10–1010UnitVVVVmAmAµAµAµAA0~A2, CS, EOP, IOR, IOW, RESET(Ta=25°C)

SymbolVIHVILIIHIILCharacteristicInput High VoltageInput Low VoltageInput High LeakageInput Low LeakageCondition——VIH=5.25VVIL=VSSMin.2.0VSS–0.510–10Max.VDD+0.50.8——UnitVVµAµADRQ, IRQ, READY,SymbolVOHVOLIOHIOLCharacteristicOutput High VoltageOutput Low VoltageOutput High CurrentOutput Low CurrentConditionIOH=–4.0mAIOL=8.0mAVOH=VDD–0.5VVOL=0.4VMin.2.4VSS–4.08.0Max.VDD0.4——UnitVVmAmA914th July ’97

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Timing Diagram

Initiator Send

Namet1t2t3t4t5t6DescriptionSCSI Data setup time to ACK activeData Bus held time from IOW inactiveIOW active timeDACK active, to DRQ inactiveACK active to next DRQ activeEOP active timeMin.401030——30Max.———2045—Unitnsnsnsnsnsns元器件交易网www.cecb2b.comHT6576AInitiator Receive

Namet1t2t3t4t5t6t7t8t9t10DescriptionIOR inactive to next REQ activeREQ active to ACK activeIOR inactive to ACK inactiveACK inactive timeData Bus hold time from IOR inactiveData Bus valid time from IOR activeREQ active to DRQ activeDACK active to DRQ inactiveDACK inactive to next DRQ activeEOP active timeMin.5050105010———2030Max.—————202520——Unitnsnsnsnsnsnsnsnsnsns1114th July ’97

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Target Send (Non-block mode)Namet1t2t3t4t5t6t7t8t9DescriptionSCSI data hold time from IOW inactiveSCSI data setup time to REQ activeACK active to REQ inactiveData Bus setup time to IOW inactiveData Bus hold time from IOW inactiveIOW active timeDACK active to DRQ inactiveIOW inactive to DACK inactiveACK active to next DRQ activeMin.—40—101030—0—Max.30—30———20—45Unitnsnsnsnsnsnsnsnsns元器件交易网www.cecb2b.com

Target Receive (Non-block mode)

Namet1t2t3t4t5t6t7t8DescriptionACK inactive to next REQ activeACK active to REQ inactiveIOR inactive to next REQ activeData Bus setup time to IOR activeData Bus hold time from IOR inactiveIOR active time DACK active to DRQ inactiveIOR inactive to DACK inactiveMin.50—50—1030—0Max.—30—20——20—Unitnsnsnsnsnsnsnsns元器件交易网www.cecb2b.comHT6576APIO Timingt1D7~0t2t3t2A2~0CSt4t4IORIOWRESETDACKDRQNamet1t2t3t4DescriptionData valid time from IOR activeData hold time from IOR inactiveData setup time to IOW inactiveIOR or IOW active timeMin.—101030Max.20———Unitnsnsnsns1414th July ’97