FEATURES
Compensates cables to 300 meters for wideband video Fast rise and fall times
4.9 ns with 2 V step @ 150 meters of UTP cable 8.0 ns with 2 V step @ 300 meters of UTP cable 55 dB peak gain at 100 MHz
Two frequency response gain adjustment pins High frequency peaking adjustment (VPEAK) Broadband flat gain adjustment (VGAIN) Pole location adjustment pin (VPOLE)
Compensates for variations between cables Can be optimized for either UTP or coaxial cable DC output offset adjust (VOFFSET) Low output offset voltage: 24 mV
Two on-chip comparators with hysteresis
Can be used for common-mode sync extraction Available in 40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Keyboard-video-mouse (KVM) Digital signage
RGB video over UTP cables
Professional video projection and distribution HD video
Security video
GENERAL DESCRIPTION
The AD8123 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of UTP and coaxial cables up to 300 meters in length. Various gain stages are summed together to best approximate the inverse frequency response of the cable. Logic circuitry inside the AD8123 controls the gain functions of the individual stages so that the lowest noise can be achieved at short-to-medium cable lengths. This technique optimizes its performance for low noise, short-to-medium range applications, while at the same time provides the high gain bandwidth required for long cable equalization (up to 300 meters). Each channel features a high impedance
differential input that is ideal for interfacing directly with the cable. The AD8123 has three control pins for optimal cable compensation, as well as an output offset adjust pin. Two voltage-controlled pins are used to compensate for different cable lengths; the VPEAK pin controls the amount of high frequency peaking and the VGAIN pin adjusts the broadband flat gain, which compensates for the low frequency flat cable loss.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Triple Differential Receiver with Adjustable Line Equalization
AD8123
FUNCTIONAL BLOCK DIAGRAM
VPEAKVPOLEVOFFSETVGAINAD8123–INROUT+INRR–INGOUTG+ING–INBOUTB+INB–INCMP1OUT+INCMP1CMP1–INCMP210+INOUTCMP20-CMP241860
Figure 1.
For added flexibility, an optional pole adjustment pin, VPOLE, allows movement of the pole locations, allowing for the compensation of different gauges and types of cable as well as variations between different cables and/or equalizers. The VOFFSET pin allows the dc voltage at the output to be adjusted, adding flexibility for dc-coupled systems.
The AD8123 is available in a 6 mm × 6 mm, 40-lead LFCSP and is rated to operate over the extended temperature range of −40°C to +85°C.
AFTER 300 METER CAT-5 CABLEUXGA RESOLUTION IMAGEAFTER 300 METER CAT-5 CABLEUXGA RESOLUTION IMAGEBEFORE AD8123.AFTER AD8123.910-41860
Figure 2.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
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AD8123
Comparators...............................................................................11 Sync Pulse Extraction Using Comparators.............................12 Using the VPEAK, VPOLE, VGAIN, and VOFFSET Inputs...................12 Using the AD8123 with Coaxial Cable....................................13 Driving 75 Ω Video Cable With the AD8123........................13 Driving a Capacitive Load.........................................................13 Filtering the RGB Outputs........................................................13 Power Supply Filtering...............................................................14 Layout and Power Supply Decoupling Considerations.........14 Input Common-Mode Range...................................................14 Small Signal Frequency Response............................................15 Power-Down...............................................................................15 Outline Dimensions.......................................................................16 Ordering Guide...............................................................................16
TABLE OF CONTENTS
Features..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................5 Thermal Resistance......................................................................5 ESD Caution..................................................................................5 Pin Configuration and Function Description..............................6 Typical Performance Characteristics.............................................7 Theory of Operation......................................................................10 Input Common-Mode Voltage Range Considerations.........10 Applications Information..............................................................11 Basic Operation..........................................................................11
REVISION HISTORY
8/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
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AD8123
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK, VGAIN, and VPOLE are set to recommended settings shown in Figure 17, unless otherwise noted. Table 1.
Parameter Conditions in Typ ax Unit PEAKING PERFORMANCE (NO CABLE) Peak Frequency VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 1 V 100 MHz VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 2 V 105 MHz Peak Gain VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 1 V 45 dB VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 2 V 55 dB DYNAMIC PERFORMANCE 10% to 90% Rise/Fall Time VOUT = 2 V step, 150 meters Cat-5 4.9 ns VOUT = 2 V step, 300 meters Cat-5 8.0 ns Settling Time to 2% VOUT = 2 V step, 150 meters Cat-5 36 ns VOUT = 2 V step, 300 meters Cat-5 106 ns –3 dB Large Signal Bandwidth VOUT = 1 V p-p, <10 meters Cat-5 120 MHz VOUT = 2 V p-p, <10 meters Cat-5 110 MHz VOUT = 2 V p-p, 150 meters Cat-5 78 MHz VOUT = 2 V p-p, 300 meters Cat-5 43 MHz Integrated Output Voltage Noise 150 meter setting, integrated to 160 MHz 2.5 mV rms 300 meter setting, integrated to 160 MHz 24 mV rms INPUT DC PERFORMANCE
MMInput Voltage Range −IN and +IN ±3.0 V Maximum Differential Voltage Swing 4 V p-p Voltage Gain ΔVO/ΔVI, VGAIN set for 0 meters of cable 1 V/V Common-Mode Rejection Ratio (CMRR) At dc, VPEAK = VGAIN = VPOLE = 0 V −86 dB At dc, VPEAK = VGAIN = VPOLE = 2 V −67 dB At 1 MHz, VPEAK = VGAIN = VPOLE = 2 V −52 dB Input Resistance Common mode 4.4 MΩ Differential 3.7 MΩ Input Capacitance Common mode 1.0 pF Differential 0.5 pF Input Bias Current 2.4 μA VOFFSET Pin Current 28.9 μA VGAIN Pin Current 0.5 μA VPEAK Pin Current 0.4 μA VPOLE Pin Current 0.4 μA ADJUSTMENT PINS VPEAK Input Voltage Range Relative to GND 0 to 2 V VPOLE Input Voltage Range Relative to GND 0 to 2 V VGAIN Input Voltage Range Relative to GND 0 to 2 V VOFFSET to OUT Gain OUT/VOFFSET, range limited by output swing 1 V/V Maximum Flat Gain VGAIN = 2 V 2 dB OUTPUT CHARACTERISTICS Output Voltage Swing 150 Ω load −3.75 to +3.69 V 1 kΩ load −3.66 to +3.69 V Output Offset Voltage Referred to output, VPEAK = VGAIN = VPOLE = 0 V 24 mV Referred to output, VPEAK = VGAIN = VPOLE = 2 V 32 mV Output Offset Voltage Drift Referred to output 33 μV/°C
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AD8123
Parameter Conditions in Typ ax Unit POWER SUPPLY Operating Voltage Range ±4.5 ±5.5 V Positive Quiescent Supply Current 132 mA Negative Quiescent Supply Current 126 mA Supply Current Drift, ICC/IEE 80 μA/°C Positive Power Supply Rejection Ratio DC, referred to output −51 dB Negative Power Supply Rejection Ratio DC, referred to output −63 dB Power Down, VIH (Minimum) Minimum Logic 1 voltage 1.1 V Power Down, VIL (Maximum) Maximum Logic 0 voltage 0.8 V Positive Supply Current, Powered Down VPEAK = VGAIN = VPOLE = 0 V 1.1 μA Negative Supply Current, Powered Down VPEAK = VGAIN = VPOLE = 0 V 0.7 μA COMPARATORS Output Voltage Levels VOH/VOL 3.33/0.043 V Hysteresis VHYST 70 mV Propagation Delay tPD, LH/tPD, HL 17.5/10.0 ns Rise/Fall Times tRISE/tFALL 9.3/9.3 ns Output Resistance 0.03 Ω OPERATING TEMPERATURE RANGE −40 +85 °C
MM
Rev. 0 | Page 4 of 16
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AD8123
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the
Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage 11 V power is the voltage between the supply pins (VS) times the Power Dissipation See Figure 3quiescent current (IS). The power dissipation due to each load Input Voltage (any input) VS− − 0.3V to VS+ + 0.3V current is calculated by multiplying the load current by the Storage Temperature Range −65°C to +125°C voltage difference between the associated power supply and the Operating Temperature Range −40°C to +85°C output voltage. The total power dissipation due to load currents Lead Temperature (Soldering, 10 sec) 300°C is then obtained by taking the sum of the individual power Junction Temperature 150°C dissipations. RMS output voltages must be used when dealing
with ac signals. Stresses above those listed under Absolute Maximum Ratings Table 2.
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Airflow reduces θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a solid plane (usually the ground plane) to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 40-lead LFCSP (29°C/W) on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a PCB plane. θJA values are approximations.
76543210–40THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air. Table 3. Thermal Resistance with the Underside Pad Connected to the Plane
Package Type/PCB Type 40-Lead LFCSP/4-Layer
θJA29 Unit °C/W
MAXIMUM POWER DISSIPATION (W)Maximum Power Dissipation
The maximum safe power dissipation in the AD8123 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8123. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure.
–20020406080
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
AMBIENT TEMPERATURE (°C)ESD CAUTION
06814-025 Rev. 0 | Page 5 of 16
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AD8123
PIN CONFIGURATION AND FUNCTION DESCRIPTION
AD8123TOP VIEW(Not to Scale)NCGND–INB+INBVS+–ING+INGVS––INR+INR40393837363534333231NC+INCMP1–INCMP1OUTCMP1VS+_CMPOUTCMP2–INCMP2+INCMP2VS–_CMPNC1234567101230292827262524232221NCVS+PDVPOLEVPEAKVGAINGNDVOFFSETVS–NCNC = NO CONNECT06814-002NOTES1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO A PCB PLANE TO ACHIEVE SPECIFIED THERMAL RESISTANCE.VS–OUTBVS+VS–OUTGVS+VS–OUTRVS+NC11121314151617181920
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic 1, 10, 20, 21, 30, 40 NC 2 +INCMP13 −INCMP14 OUTCMP15 VS+_CMP 6 OUTCMP27 −INCMP28 +INCMP29 VS−_CMP 11, 14, 17, 22, 33 VS−12 OUTB13, 16, 19, 29, 36 VS+15 OUTG18 OUTR23 VOFFSET24, 39 GND 25 VGAIN26 VPEAK27 VPOLE28 PD 31 +INR32 −INR34 +ING35 −ING37 +INB38 −INBExposed Underside Pad Description No Internal Connection. Positive Input, Comparator 1. Negative Input, Comparator 1. Output, Comparator 1. Positive Power Supply, Comparator. Must be connected to VS+. Output, Comparator 2. Negative Input, Comparator 2. Positive Input, Comparator 2. Negative Power Supply, Comparator. Must be connected to VS−. Negative Power Supply, Equalizer Sections. Output, Blue Channel. Positive Power Supply, Equalizer Sections. Output, Green Channel. Output, Red Channel. Output Offset Control Voltage. Signal Ground Reference. Broadband Flat Gain Control Voltage. Equalizer High Frequency Boost Control Voltage. Equalizer Pole Location Adjustment Control Voltage. Power Down. Positive Input, Red Channel. Negative Input, Red Channel. Positive Input, Green Channel. Negative Input, Green Channel. Positive Input, Blue Channel. Negative Input, Blue Channel. Thermal Plane Connection. Connect to any PCB plane with voltage between VS+ and VS−. Rev. 0 | Page 6 of 16
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AD8123
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK, VGAIN, and VPOLE are set to recommended settings shown in Figure 17, unless otherwise noted.
4321VGAIN = 0VVPOLE = 0VVO = 1V p-p3210–1–2–3–4–5–6–7–8–9VO = 2V p-pGAIN (dB)–1–2–3–4–5–6100kVGAIN = 0VVGAIN = 1VVGAIN = 2V06814-003GAIN (dB)0–10–111M10MFREQUENCY (Hz)100M50m100m150m200m300m1M10MFREQUENCY (Hz)100M06814-006–12100k
Figure 5. Frequency Response for Various VGAIN Without Cable
60VGAIN = 0.6VVPOLE = 2VVO = 1V p-pFigure 8. Equalized Frequency Response for Various Cable Lengths
120VO = 2V p-p1004020BANDWIDTH (MHz)VPEAK = 0VVPEAK = 1VVPEAK = 2V1M10MFREQUENCY (Hz)100M06814-00480GAIN (dB)060–2040–4020050100150200250300
CABLE LENGTH (meters)06814-00706814-008–60100k0
Figure 6. Frequency Response for Various VPEAK Without Cable
403020106VGAIN = 0.6VVPEAK = 1VVO = 1V p-pFigure 9. Equalized −3 dB Bandwidth vs. Cable Length
VGAIN = 0.6VVPEAK = 0VVPOLE = 0V42GAIN (dB)0–10–20–30–40–50–60100kVPOLE = 0VVPOLE = 1VVPOLE = 2V1M10MFREQUENCY (Hz)100M06814-005VOLTAGE (V)0–2–4INPUTOUTPUT–6050100150200250300350400450500
TIME (ns)
Figure 7. Frequency Response for Various VPOLE Without Cable
Figure 10. Overdrive Recovery
Rev. 0 | Page 7 of 16
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AD8123
1.550m150m300m
1.550m150m300m1.01.0OUTPUT VOLTAGE (V)OUTPUT VOLTAGE (V)0.50.500–0.5–0.5–1.0–1.006814-009050100150200250300350400450500012345TIME (µs)6710TIME (ns)
06814-012–1.5–1.5
Figure 11. Pulse Response for Various Cable Lengths (2 MHz)
10000
0m150m300mFigure 14. Pulse Response for Various Cable Lengths (100 kHz)
30INTEGRATED OUTPUT VOLTAGE NOISE FROM100kHz TO 160MHz (mV rms)06814-010OUTPUT VOLTAGE NOISE (nV/Hz)25100020151001051M10MFREQUENCY (Hz)
100M5075100125150175200225250275300
Figure 12. Output Voltage Noise vs. Frequency for Various Cable Length
20100–10–20VGAIN = 0V, VPEAK = 0V, VPOLE = 0VVGAIN = 1.85V, VPEAK = 1.65V, VPOLE = 1.75VCABLE LENGTH (meters)06814-01310100k025
Figure 15. Integrated Output Voltage Noise vs. Cable Length
20100–10CROSSTALK (dB)VGAIN = 0V, VPEAK = 0V, VPOLE = 0VVGAIN = 1.85V, VPEAK = 1.65V, VPOLE = 1.75VCMRR (dB)–20–30–40–50–60–70–30–40–50–60–70–8006814-0111M10MFREQUENCY (Hz)100M1M10MFREQUENCY (Hz)100M06814-014–90100k–80100k
Figure 13. CMRR vs. Frequency Figure 16. Crosstalk vs. Frequency
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2.01.81.6CONTROL VOLTAGE (V)CONTROL VOLTAGE (V)AD8123
VPEAKVPOLEVGAIN2.01.81.61.41.21.00.80.60.40.206814-015VPEAKVPOLEVGAIN1.41.21.00.80.60.40.202550751001251501752002252502753005075100125150175200225250275300CABLE LENGTH (meters)
CABLE LENGTH (meters)06814-016025
Figure 17. Recommended Settings for UTP Cable
Figure 18. Recommended Settings for Coaxial Cable
Rev. 0 | Page 9 of 16
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AD8123
The AD8123 is designed such that systems that use short-to-medium-length cables do not pay a noise penalty for excess gain that they do not require. The high gain is only available for longer length systems where it is required. This feature is built into the VPEAK control and is transparent to the user.
Two comparators are provided on-chip that can be used for sync pulse extraction in systems that use sync-on-common mode encoding. Each comparator has very low output impedance and can therefore be used in a source-only cable termination scheme by placing a series resistor equal to the cable characteristic impedance directly on the comparator output. Additional details are provided in the Applications Information section.
THEORY OF OPERATION
The AD8123 is a unity-gain, triple, wideband, low noise analog line equalizer that compensates for losses in UTP and coaxial cables up to 300 meters in length. The 3-channel architecture is targeted at high resolution RGB applications but can be used in HD YPbPr applications as well.
Three continuously adjustable control voltages, common to the RGB channels, are available to the designer to provide compensation for various cable lengths as well as for variations in the cable itself. The VPEAK input is used to control the amount of high frequency peaking. VPEAK is the primary control that is used to compensate for frequency and cable-length dependent, high frequency losses that are present due to the skin effect of the cable. A second control pin, VGAIN, is used to adjust broadband gain to compensate for low frequency flat losses present in the cable. A third control, VPOLE, is used to move the positions of the equalizer poles and can be linearly derived from VPEAK, as illustrated in the Typical Performance Characteristics and Applications Information sections, for UTP and coaxial cables. Finally, an output offset adjust control, VOFFSET, allows the designer to shift the output dc level.
The AD8123 has a high impedance differential input that makes termination simple and allows dc-coupled signals to be received directly from the cable. The AD8123 input can also be used in a single-ended fashion in coaxial cable applications. For differential systems that require very high CMRR, a triple differential receiver, such as the AD8143 or AD8145, can be placed in front of the AD8123.
The AD8123 has a low impedance output that is capable of driving a 150 Ω load. For systems where the AD8123 has to drive a high impedance capacitive load, it is recommended that a small series resistor be placed between the output and load to buffer the capacitance. The resistor should not be so large as to reduce the overall bandwidth to an unacceptable level.
INPUT COMMON-MODE VOLTAGE RANGE CONSIDERATIONS
When using the AD8123 as a receiver, it is important to ensure that its input common-mode voltage stays within the specified range. The received common-mode level is calculated by adding the common-mode level of the driver, the single-ended peak amplitude of the received signal, the amplitude of any sync pulses, and the other induced common-mode signals, such as ground shifts between the driver and the AD8123 and pickup from external sources, such as power lines and fluorescent lights. See the Applications Information section for more details.
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AD8123
The comparator outputs have nearly 0 Ω output impedance and are designed to drive source-terminated transmission lines. The source termination technique uses a resistor in series with each comparator output such that the sum of the comparator source resistance (≈0 Ω) and the series resistor equals the transmission line characteristic impedance. The load end of the transmission line is high impedance. When the signal is launched into the source termination, its initial value is one-half of its source value because its amplitude is divided by two in the voltage divider formed by the source termination and the transmission line. At the load, the signal experiences nearly 100% positive reflection due to the high impedance load and is restored to nearly its full value. This technique is commonly used in PCB layouts that involve high speed digital logic.
Figure 19 shows how to apply the comparators with source termination when driving a 50 Ω transmission line that is high impedance at its receive end.
HIGH-ZAPPLICATIONS INFORMATION
BASIC OPERATION
The AD8123 is easy to apply seeing that it contains everything on-chip that is needed for cable loss compensation. Figure 20 shows a basic application circuit (power supplies not shown) with common-mode sync pulse extraction that is compatible with the common-mode sync pulse encoding technique used in the AD8134, AD8147, and AD8148 triple differential drivers. If sync extraction is not required, the terminations can be single 100 Ω resistors, and the comparator inputs can be left floating. In Figure 20, the AD8123 is feeding a high impedance input, such as a delay line or crosspoint switch, and the additional gain of two that makes up for double termination loss is not required.
COMPARATORS
In addition to general-purpose applications, the two on-chip comparators can be used to extract video sync pulses from the received common-mode voltages or to receive differential digital information. Built-in hysteresis helps to eliminate false triggers from noise. The Sync Pulse Extraction Using Comparators section describes the sync extraction details.
49.9ΩZ0 = 50Ω06814-021
Figure 19. Using Comparator with Source Termination
ANALOGCONTROLINPUTS26272523VPEAKVPOLEVGAINVOFFSETPDRED1832GREEN1535GREEN VIDEO OUTRED VIDEO OUTAD8123POWER DOWN28CONTROL31RECEIVEDRED VIDEO49.9Ω49.9ΩRECEIVEDGREEN VIDEO49.9Ω49.9Ω34RECEIVEDBLUE VIDEO49.9Ω49.9Ω3738BLUE12BLUE VIDEO OUT1kΩ1kΩBLUE CMV2RED CMV3814HSYNC OUT47pF47pF24, 3906814-020GREENCMV475Ω72GND REFERENCE6VSYNC OUT
Figure 20. Basic Application Circuit with Common-Mode Sync Extraction
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AD8123
In some cases, as would likely be with automatic control, the VPEAK control is derived from a low impedance source, such as an op amp. Figure 21 shows how to derive VPOLE from VPEAK in a UTP application according to the recommended curves shown in Figure 17, when VPEAK originates from a low impedance source. Clearly, the 5 V supply must be clean to provide a clean VPOLE voltage.
20Ω5VVPEAK5.11kΩ14kΩVPOLE ≈8.25kΩVPEAK2VPEAKSYNC PULSE EXTRACTION USING COMPARATORS
The AD8123 is useful in many systems that transport computer video signals, which are typically comprised of red, green, and blue (RGB) video signals and separate horizontal and vertical sync signals. Because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the RGB signals. The AD8134, AD8147, and AD8148 triple differential drivers are natural complements to the AD8123 seeing that they perform the sync pulse encoding with the necessary circuitry on-chip. The sync encoding equations follow:
RedVCM=GreenVCM
K
V−H (1) 2The 20 Ω series resistor in the VPEAK path provides capacitive
load buffering for the op amp. This value can be modified, K
=−2V (2) depending on the actual capacitive load. 2
[]
Figure 21. Deriving VPOLE from VPEAK with Low-Z Source for UTP Cable
[]BlueVCM=
where:
Red VCM, Green VCM, and Blue VCM are the transmitted common-mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the driver. V and H are the vertical and horizontal sync pulses, defined with a weight of −1 when the pulses are in their low states, and a weight of +1 when they are in their high states.
The AD8134 and AD8146/AD8147/AD8148 data sheets contain further details regarding the encoding scheme. Figure 20 illustrates how the AD8123 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the RGB common-mode voltages by the aforementioned drivers.
In automatic equalization circuits that place the control voltages K
V+H (3) inside feedback loops, attention must be paid to the poles 2
produced by the summing resistors and load capacitances.
[]The peaking can also be adjusted by a mechanical or digitally controlled potentiometer. In these cases, if the resistance of the potentiometer is a couple of orders of magnitude lower than the values of the resistors used to develop VPOLE, its resistance can be ignored. Figure 22 shows how to use a 500 Ω potentiometer with the resistor values shown in Figure 21 scaled up by a factor of 10.
5V750Ω500Ω51.1kΩVPE5V140kΩVPOLE ≈82.5kΩVPEAK2
Figure 22. Deriving VPOLE from VPEAK with Potentiometer for UTP Cable
USING THE VPEAK, VPOLE, VGAIN, AND VOFFSET INPUTS
The VPEAK input is the main peaking control and is used to compensate for the low-pass roll-off in the cable response. The VPOLE input is a secondary frequency response shaping control that shifts the positions of the equalizer poles. The VGAIN input controls the wideband flat gain and is used to compensate for the low frequency cable loss that is nominally flat. The VOFFSET input is used to produce an offset at the AD8123 output. The output offset is equal to the voltage applied to the VOFFSET input, limited by the output swing limits.
The VPEAK and VPOLE controls can be used independently or they can be coupled together to form a single peaking control. While Figure 17 and Figure 18 show recommended settings vs. cable length, designers may find other combinations that they prefer. These two controls give designers extra freedom, as well as the ability to compensate for different cable types (such as UTP and coaxial cable), as opposed to having only a single frequency shaping control.
Many potentiometers have wide tolerances. If a wide tolerance potentiometer is used, it may be necessary to change the value of the 750 Ω resistor to obtain a full swing for VPEAK.
The VGAIN input is essentially a contrast control and can be set by adjusting it to produce the correct amplitude of a known test signal (such as a white screen) at the AD8123 output.
VGAIN can also be derived from VPEAK according to the linear relationships shown in Figure 17 and Figure 18. Figure 23 shows how to derive VPOLE and VGAIN from VPEAK in a UTP application that originates from a low-Z source.
20Ω5VVPEAK5.11kΩ14kΩVPOLE ≈
8.25kΩ2
+ 0.9V
VPEAK5V5.11kΩ60.4kΩ133kΩ06814-028VGAIN ≈ 0. × VPEAK + 0.38V
Figure 23. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for UTP Cable
Rev. 0 | Page 12 of 16
06814-027+ 0.9V06814-026+ 0.9V元器件交易网www.cecb2b.com
AD8123
The other option is to include a triple gain-of-2 buffer, such as the ADA4862-3, on the AD8123 RGB outputs, as shown in Figure 26 for one channel (power supplies not shown). The ADA4862-3 provides the gain of 2 that compensates for the double-termination loss.
ONE CHANNEL OF ADA4862-3ONE VIDEOOUTPUTFROM AD8123USING THE AD8123 WITH COAXIAL CABLE
The VPOLE control allows the AD8123 to be used with other types of cable, including coaxial cable. Figure 18 presents the recommended settings for VPEAK, VPOLE, and VGAIN when the AD8123 is used with good quality 75 Ω video cable. Figure 24 shows how to derive VPOLE and VGAIN from VPEAK in a coaxial cable application where VPEAK originates from a low-Z source.
20ΩVPEAK75Ω500Ω500ΩZ0 = 75Ω75Ω06814-022VPEAK5.11kΩ24.3kΩ47.5kΩVPOLE ≈ 0.76 × VPEAK – 0.41V
Figure 26. Using ADA4862-3 on AD8123 Outputs
1.16kΩ20kΩ10kΩ1.24kΩ–5VDRIVING A CAPACITIVE LOAD
VGAIN ≈ 1.06 × VPEAK – 0.62V06814-029+5V
Figure 24. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for Coaxial Cable
When driving a high impedance capacitive input, it is necessary to place a small series resistor between each of the three AD8123 video outputs and the load to buffer the input capacitance of the device being driven. Clearly, the resistor value must be small enough to preserve the required bandwidth.
The op amp in the circuit that develops VGAIN is required to insert the offset of −0.62 V with a gain from VPEAK to VGAIN that is close to unity. A passive offset circuit would require an offset injection voltage that is much larger in magnitude than the available −5 V supply. Clearly, the VGAIN control voltage can also be developed independently.
The AD8123 differential input can accept signals carried over unbalanced cable, as shown in Figure 25, for an unbalanced 75 Ω coaxial cable termination.
INPUT FROM75Ω CABLEAD8123INPUT STAGE06814-030FILTERING THE RGB OUTPUTS
In some cases, it is desirable to place low-pass filters on the
AD8123 video outputs to reduce high frequency noise. A 3-pole Butterworth filter with cutoff frequency in the neighborhood of 140 MHz is sufficient in most applications. Figure 27 and Figure 28 present filters for the high impedance load case (driving a delay line, crosspoint switch, ADA4862-3) and the double-termination case (75 Ω source and load resistances), respectively. In the high impedance load case, the load capacitance must be absorbed in the capacitor that is placed across the load. For example, in Figure 27, if the high-Z load were the input to an ADA4862-3, which has an input capacitance of 2 pF, the filter capacitor value in parallel with the input would be 15 pF to obtain a total of 17 pF.
HIGH-ZAD8123OUTPUT75Ω
100Ω150nH5.6pFFigure 25. Terminating a 75 Ω Cable
DRIVING 75 Ω VIDEO CABLE WITH THE AD8123
When the RGB outputs must drive a 75 Ω line rather than a high impedance load, an additional gain of two is required to make up for the double termination loss (75 Ω source and load terminations). There are two options available for this. One option is to place the additional gain of 2 at the drive end by using the AD8148 triple differential driver to drive the cable. The AD8148 has a fixed gain of 4 instead of the usual gain of 2 and thereby provides the required additional gain of 2 without having to add additional amplifiers to the signal chain. The AD8148 also contains sync-on-common-mode encoding. If sync-on-common-mode is not required, it can be deactivated on the AD8148 by connecting its SYNC LEVEL input to ground.
17pF*06814-023
Figure 27. 140 MHz Low-Pass Filter on AD8123 Output Feeding High-Z Load
*INPUT CAPACITANCE OF LOAD MUST BE ABSORBED INTO THIS VALUE.
AD8123OUTPUT75Ω180nH15pF15pFZ0 = 75Ω06814-02475Ω
Figure 28. 135 MHz Low-Pass Filter on AD8123 Output Feeding
Doubly Terminated Load
These filters are by no means the only choices but are presented here as examples. In the high-Z load case, it is important to keep the filter source resistance large enough to buffer the capacitive loading presented by the first capacitor in the filter.
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AD8123
0–20OUTPUT RESPONSE (dB)POWER SUPPLY FILTERING
External power supply filtering between the system power supplies and the AD8123 is required in most applications to prevent supply noise from contaminating the received signal as well as to prevent unwanted feedback through the supplies that could cause instability. Figure 29 shows that the AD8123 power supply rejection decreases with increasing frequency. These plots are for the lowest control settings and shift upward as the peaking is increased.
100–10VGAIN = 0VVPEAK = 0VVPOLE = 0V–40–60–80–100100k1M10M100M
Figure 31. Power Supply Filter Frequency Response in a 50 Ω System
FREQUENCY (Hz)PSRR (dB)–20–30–40–50–60100kLAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to when designing with the AD8123. A solid ground plane is required and controlled impedance traces should be used when interconnecting the high speed signals. Source termination resistors on all of the outputs must be placed as close as possible to the output pins.
The exposed paddle on the underside of the AD8123 must be connected to a pad that connects to at least one PCB plane. Several thermal vias should be used to make the connection between the pad and the plane(s).
High quality 0.1 μF power supply decoupling capacitors should be placed as close as possible to all of the supply pins. Small surface-mount ceramic capacitors should be used for these, and tantalum capacitors are recommended for bulk supply decoupling.
+PSRR–PSRR1M10MFREQUENCY (Hz)100M06814-017
Figure 29. AD8123 PSRR vs. Frequency
A suitable filter that uses a surface-mount ferrite bead is shown in Figure 30, and its frequency response is shown in Figure 31. Because the frequency response was taken using a 50 Ω network analyzer and with only one 0.1 μF capacitor on the AD8123 side, the actual amount of rejection provided by the filter in a real-world application will be different from that shown in Figure 31. The general shape of the rejection curve, however, will match Figure 31, providing substantially increased overall PSRR from approximately 5 MHz to 500 MHz, where it is most needed. One filter is required on each of the two supplies (not one filter per supply pin).
FAIR-RITE2743021447SYSTEMSUPPLYTO AD8123*0.1µF4700pF4700pF06814-031INPUT COMMON-MODE RANGE
Most applications that use the AD8123 as a receiver use a driver (such as one from the AD8146/AD8147/AD8148 family, the AD8133, or the AD8134) powered from ±5 V supplies. This places the common-mode voltage on the line nominally at 0 V relative to the ground potential at the driver and provides
optimum immunity from any common-mode anomalies picked up along the cable (including ground shifts between the driver and receiver ends). In many of these applications, the AD8123 input voltage range of typically ±3.0 V is sufficient. If wider input range is required, the AD8143 triple receiver (input
common-mode range equals ±10.5 V on ±12 V supplies) may be placed in front of the AD8123. Figure 32 illustrates how this is done for one channel.
*ALL AD8123 SUPPLY PINS ARE INDIVIDUALLYDECOUPLED WITH A 0.1µF CAPACITOR.
Figure 30. Power Supply Filter
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ONEAD8143 CHANNELPOWER SUPPLIES =±12VRECEIVEDSIGNALONEAD8123INPUT+5V100Ω49.9Ω23AD8123
SMALL SIGNAL FREQUENCY RESPONSE
Though the AD8123 large signal frequency response
(VO = 1 V p-p) is of most concern, occasionally designers are interested in the small signal frequency response. The AD8123 frequency response for VO = 300 m V p-p is shown in Figure 33 for 200 meter and 300 meter cable lengths.
3210–1–2300 METERS–3–4–5–6–7–8–9–10–110.111010006814-03206814-033HBAT-540C1–5VVO = 300mV p-p200 METERSFigure 32. Optional Use of AD8143 in Front of AD8123 for
Wide Input Common-Mode Range
The Schottky diodes are required to protect the AD8123 from any AD8143 outputs that may exceed the AD8123 input limits. The 49.9 Ω resistor limits the fault current and produces a pole at approximately 800 MHz with the effective diode capacitance of 3 pF and the AD8123 input capacitance of 1 pF. The pole drops the response by only 0.07 dB at 100 MHz and therefore has a negligible effect on the signal.
When using a single 5 V supply on the driver side, the
common-mode voltage at the driver is typically midsupply, or VCM = 2.5 V. The largest received differential video signal is approximately 700 mV p-p, and this therefore adds 175 mVPEAK to the common-mode voltage, resulting in a worst-case peak voltage of 2.675 V on an AD8123 input (presuming there is no ground shift between driver and receiver). This is within the AD8123 input voltage swing limits, and such a system works well as long as the difference in ground potential between driver and receiver does not cause the input voltage swing to exceed its specified limits.
When used, common-mode sync signals are generally applied with a peak deviation of 500 mV and thereby increase the common-mode level from 2.675 V to 3.175 V. This common-mode level exceeds the specified input voltage swing limits of ±3.0 V; therefore, the AD8123 cannot be used with a system that uses common-mode sync encoding with 500 mV sync peak deviation and 2.5 V common-mode line level. While it is possible to operate a driver powered from a single 5 V supply at a common-mode voltage of <2.5 V to obtain a received voltage swing that is within the specified limits, there is not much margin for other shifts in the common-mode level due to interference pickup and differing ground potentials. There are two ways to increase the common-mode range of the overall system. One is to power the driver from ±5 V supplies, and the other is to place an AD8143 in front of the AD8123, as shown in Figure 32. These techniques may be combined or applied separately.
GAIN (dB)–120.01
Figure 33. Small Signal Frequency Response for Various Cable Lengths
FREQUENCY (MHz)POWER-DOWN
The power-down feature is intended to be used to reduce power consumption when a particular device is not in use and does not place the output in a high-Z state when asserted. The input logic levels and supply current in power down mode are presented in the Power Supply section of Table 1.
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AD8123
OUTLINE DIMENSIONS
6.00BSC SQ0.60 MAX0.60 MAX2928401PIN 1INDICATOR4.454.30 SQ4.15PIN 1INDICATORTOPVIEW5.75BCS SQ0.50BSCEXPOSEDPAD(BOTTOM VIEW)0.500.400.300.80 MAX0.65 TYP0.05 MAX0.02 NOMCOPLANARITY0.080.20 REF201911100.25 MIN4.50REF1.000.850.80SEATINGPLANE12° MAXCOMPLIANTTO JEDEC STANDARDS MO-220-VJJD-2080107-A0.300.230.18
Figure 34. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm, Very Thin Quad
(CP-40-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8123ACPZ-R21AD8123ACPZ-R71AD8123ACPZ-RL1
1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ 40-Lead LFCSP_VQ Package Option CP-40-4 CP-40-4 CP-40-4
Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06814-0-8/07(0)
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